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VIA unveils Isaiah processor architecture – 64-bit superscalar

VIA Technologies today announced details about VIA Isaiah, its new architecture for x86 processors.

This architecture combines 64-bit superscalar speculative microarchitecture with out-of-order instruction execution, high performance multimedia computing and a new virtual machine architecture. The first generation of Isaiah-based products will be pin-to-pin compatible with the VIA C7 processor family.

Processors based on VIA Isaiah architecture will use 65nm technical process. Together with new and enhanced power and heat management capabilities, this will ensure the best performance / watt on the market and support the development of a range of computing products such as green, quiet and small desktop PCs, multimedia centers, ultra-thin and light notebooks and subnotebooks.

Key aspects of the VIA Isaiah architecture noted by the manufacturer:

  • 64-bit superscalar speculative microarchitecture with out-of-order execution of instructions. VIA Isaiah’s architecture includes a host of advanced architectural features, including layering of micro and macro operations (macro-fusion and micro-fusion) with sophisticated branch prediction system, which significantly improves processor efficiency and performance. In addition, the architecture offers a full set of 64-bit instructions with many options to support 64-bit operating systems and applications, as well as a new virtual machine structure for safer and more efficient operation of systems in virtual environments.
  • In addition to supporting 2GHz clock in early products and a high-speed, energy-efficient front side bus operating at 800-1333MHz, the VIA Isaiah architecture also has a highly efficient caching subsystem consisting of two 64KB L1 cache blocks and 1MB exclusive L2 cache with degree of associativity of 16 for more efficient optimization of the memory subsystem.
  • VIA Isaiah uses new algorithms to minimize latency and allows four addition and four multiplication operations on floating point numbers in one clock cycle. In addition, to further increase performance in multimedia applications, the architecture supports new SSE instructions and a 128-bit data channel.
  • To minimize power consumption and reduce heat dissipation, the VIA Isaiah architecture uses low-power looping techniques and, in addition to aggressive power management methods, offers support for the new C6 power state, which turns off power to caches.
  • Advanced adaptive PowerSaver technology further reduces power consumption and improves heat management. For this, for example, TwinTurbo technology is used with two PLLs, which work like an automatic transmission, allowing smooth transitions between operating states within one clock cycle. This ensures zero downtime and minimizes latency, and introduces new mechanisms for managing core temperature.
  • To improve the confidentiality, integrity and authenticity of electronic data, the VIA Isaiah architecture includes industry-leading hardware acceleration capabilities for cryptographic functions, implemented at the processor core level. VIA PadLock security features include a random number generator, AES encryption module, SHA-1 and SHA-256 hashblocks to improve data integrity, and a new dedicated “secure execution” mode. allowing you to work in a secure section of memory located directly on the chip and transmit instructions in encrypted form.

VIA Isaiah-based processors are expected to ship in the first half of 2021.

Source: VIA

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