Nanocluster silicon dioxide claims to be a dielectric for 65nm chips
As manufacturers embrace the 65nm process technology, there is a growing need for new materials that match the characteristics of the smaller structures that make up the integrated circuits.
Several companies have already introduced low-k (low-k) porous materials of 2.25 to replace traditional dielectrics. New among them is nano clustering silica (NSC). According to the source, it meets the requirements of the 65nm process technology, being able to carry out the steps of chemical mechanical polishing (CMP), attaching the lead wires and packaging the chips. The properties of NSC are such that it is possible to take advantage of the reduced value of the constant k and increase the strength of the thin film, while.
NSC material allows for multi-layer internal connections. Lead wire attachment using copper in combination with NSC does not damage internal copper connections. In terms of the combination of positive properties – mechanical strength, thermal stability and dimensional stability – NCS stands out among other materials with a low dielectric constant. Therefore, the source claims, it is expected to be widely used as an interlayer dielectric in chips manufactured at 65 nm.